/**
  ******************************************************************************
  * @file    usbpd-tcpp0203_conf.h
  * @author  MCD Application Team
  * @brief   USBPD-TCPP0203 driver configuration file.
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2022 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef USBPD_TCPP0203_CONF_H__
#define USBPD_TCPP0203_CONF_H__

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
/* Replace the header file names with the ones of the target platform */
#include "main.h"
#include "stm32g0xx_nucleo.h"
#include "stm32g0xx_ll_adc.h"
#include "stm32g0xx_ll_bus.h"
#include "stm32g0xx_ll_gpio.h"
#include "stm32g0xx_ll_rcc.h"
#include "stm32g0xx_ll_exti.h"


/** @addtogroup USBPD-TCPP0203
  * @{
  */

/** @addtogroup USBPD-TCPP0203_CONFIG
  * @{
  */

/** @addtogroup USBPD-TCPP0203_CONFIG_Exported_Constants Exported Constants
  * @{
  */

/* I2C BUS definitions */
#ifndef BUS_I2C_FREQUENCY
#define BUS_I2C_FREQUENCY                400000U /* Frequency of I2Cn = 400 kHz*/
#endif /* !BUS_I2C_FREQUENCY */

#define BUS_I2C_CLK_ENABLE()             __HAL_RCC_I2C2_CLK_ENABLE()
#define BUS_I2C_CLK_DISABLE()            __HAL_RCC_I2C2_CLK_DISABLE()
#define BUS_I2C_FORCE_RESET()            __HAL_RCC_I2C2_FORCE_RESET()
#define BUS_I2C_RELEASE_RESET()          __HAL_RCC_I2C2_RELEASE_RESET()

#define BUS_I2C_SCL_GPIO_PIN             GPIO_PIN_11
#define BUS_I2C_SCL_GPIO_PORT            GPIOA
#define BUS_I2C_SCL_GPIO_AF              GPIO_AF6_I2C2
#define BUS_I2C_SCL_GPIO_CLK_ENABLE()    __HAL_RCC_GPIOA_CLK_ENABLE()
#define BUS_I2C_SCL_GPIO_CLK_DISABLE()   __HAL_RCC_GPIOA_CLK_DISABLE()
#define BUS_I2C_SDA_GPIO_PIN             GPIO_PIN_12
#define BUS_I2C_SDA_GPIO_PORT            GPIOA
#define BUS_I2C_SDA_GPIO_AF              GPIO_AF6_I2C2
#define BUS_I2C_SDA_GPIO_CLK_ENABLE()    __HAL_RCC_GPIOA_CLK_ENABLE()
#define BUS_I2C_SDA_GPIO_CLK_DISABLE()   __HAL_RCC_GPIOA_CLK_DISABLE()

#define BUS_I2C_IRQ_N                    I2C2_IRQn
#define BUS_I2C_IRQ_HANDLER              I2C2_IRQHandler

#define BUS_I2C_POLL_TIMEOUT             0x1000U

#define VISENSE_DMA_INSTANCE            DMA1 /* Common for VSENSE and ISENSE */
#define VISENSE_DMA_CHANNEL             LL_DMA_CHANNEL_4
#define VISENSE_DMA_REQ                 LL_DMAMUX_REQ_ADC1 /* Select ADC as DMA transfer request */
#define VISENSE_DMAMUX_CHANNEL          LL_DMAMUX_CHANNEL_3 /* Channel needs to be VISENSE_DMA_CHANNEL - 1 */

#define VISENSE_ADC_INSTANCE            ADC1
#define VISENSE_ADC_COMMON              ADC12_COMMON
#define VISENSE_ADC_RANK                LL_ADC_REG_RANK_1
#define VSENSE_ADC_CHANNEL              TCPP0203_PORT0_VBUSC_ADC_CHANNEL
#define ISENSE_ADC_CHANNEL              TCPP0203_PORT0_IANA_ADC_CHANNEL
#define VISENSE_ADC_BUFFER_SIZE         2u /* Number of ADC channels used */

/**
  * @brief TCPP0203_FLGn pin
  * To be defined for each Port, protected by a TCPP0203 component
  */
#define TCPP0203_PORT0_FLG_GPIO_CLK_ENABLE()        LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOC);
#define TCPP0203_PORT0_FLG_GPIO_CLK_DISABLE()       LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOC);
#define TCPP0203_PORT0_FLG_GPIO_PORT                GPIOC
#define TCPP0203_PORT0_FLG_GPIO_PIN                 LL_GPIO_PIN_6
#define TCPP0203_PORT0_FLG_GPIO_MODE                LL_GPIO_MODE_INPUT
#define TCPP0203_PORT0_FLG_GPIO_PUPD                LL_GPIO_PULL_UP
#define TCPP0203_PORT0_FLG_SET_EXTI()               LL_EXTI_SetEXTISource(LL_EXTI_CONFIG_PORTC, LL_EXTI_CONFIG_LINE6);
#define TCPP0203_PORT0_FLG_EXTI_LINE                LL_EXTI_LINE_6
#define TCPP0203_PORT0_FLG_EXTI_ENABLE()            LL_EXTI_EnableIT_0_31(TCPP0203_PORT0_FLG_EXTI_LINE);
#define TCPP0203_PORT0_FLG_EXTI_DISABLE()           LL_EXTI_DisableIT_0_31(TCPP0203_PORT0_FLG_EXTI_LINE);
#define TCPP0203_PORT0_FLG_TRIG_ENABLE()            LL_EXTI_EnableFallingTrig_0_31(TCPP0203_PORT0_FLG_EXTI_LINE);
#define TCPP0203_PORT0_FLG_TRIG_DISABLE()           LL_EXTI_DisableFallingTrig_0_31(TCPP0203_PORT0_FLG_EXTI_LINE);
#define TCPP0203_PORT0_FLG_EXTI_IS_ACTIVE_FLAG()    LL_EXTI_IsActiveFallingFlag_0_31(TCPP0203_PORT0_FLG_EXTI_LINE)
#define TCPP0203_PORT0_FLG_EXTI_CLEAR_FLAG()        LL_EXTI_ClearFallingFlag_0_31(TCPP0203_PORT0_FLG_EXTI_LINE);
#define TCPP0203_PORT0_FLG_EXTI_IRQN                EXTI4_15_IRQn
#define TCPP0203_PORT0_FLG_EXTI_IRQHANDLER          EXTI4_15_IRQHandler
#define TCPP0203_PORT0_FLG_IT_PRIORITY              (12U)
#define TCPP0203_PORT0_FLG_GENERATE_IT()            LL_EXTI_GenerateSWI_0_31(TCPP0203_PORT0_FLG_EXTI_LINE);

/**
  * @brief TCPP0203_PWRENn pin
  */
#define TCPP0203_PORT0_ENABLE_GPIO_CLK_ENABLE()     LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOD);
#define TCPP0203_PORT0_ENABLE_GPIO_CLK_DISABLE()    LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOD);
#define TCPP0203_PORT0_ENABLE_GPIO_PORT             GPIOD
#define TCPP0203_PORT0_ENABLE_GPIO_PIN              LL_GPIO_PIN_0
#define TCPP0203_PORT0_ENABLE_GPIO_MODE             LL_GPIO_MODE_OUTPUT
#define TCPP0203_PORT0_ENABLE_GPIO_OUTPUT           LL_GPIO_OUTPUT_PUSHPULL
#define TCPP0203_PORT0_ENABLE_GPIO_PUPD             LL_GPIO_PULL_NO
#define TCPP0203_PORT0_ENABLE_GPIO_DEFVALUE()       LL_GPIO_ResetOutputPin(TCPP0203_PORT0_ENABLE_GPIO_PORT,\
                                                                           TCPP0203_PORT0_ENABLE_GPIO_PIN);
#define TCPP0203_PORT0_ENABLE_GPIO_SET()            LL_GPIO_SetOutputPin(TCPP0203_PORT0_ENABLE_GPIO_PORT,\
                                                                         TCPP0203_PORT0_ENABLE_GPIO_PIN);
#define TCPP0203_PORT0_ENABLE_GPIO_RESET()          LL_GPIO_ResetOutputPin(TCPP0203_PORT0_ENABLE_GPIO_PORT,\
                                                                           TCPP0203_PORT0_ENABLE_GPIO_PIN);

/* Definition of ADCx instance */
#define TCPP0203_PORT0_ADC_INSTANCE                 ADC2
#define TCPP0203_PORT0_ADC_CLK_ENABLE()            __HAL_RCC_ADC12_CLK_ENABLE()
#define TCPP0203_PORT0_ADC_CLK_DISABLE()           __HAL_RCC_ADC12_CLK_DISABLE()
#define TCPP0203_PORT0_ADC_FORCE_RESET()           __HAL_RCC_ADC12_FORCE_RESET()
#define TCPP0203_PORT0_ADC_RELEASE_RESET()         __HAL_RCC_ADC12_RELEASE_RESET()

/* Definition of ADCx channels */
#define TCPP0203_PORT0_IANA_ADC_CHANNEL             ADC_CHANNEL_11          /* PB0 : ADC1_IN8 */
#define TCPP0203_PORT0_VBUSC_ADC_CHANNEL            ADC_CHANNEL_7           /* PA7 : ADC1_IN7 */
#define TCPP0203_PORT0_VBUSPROV_ADC_CHANNEL         ADC_CHANNEL_2           /* PA1 : ADC12_IN2 */
#define TCPP0203_PORT0_VBUSCONS_ADC_CHANNEL         ADC_CHANNEL_7           /* PA4 : ADC2_IN7  */
#define TCPP0203_PORT0_ADCXCHANNELN                 (4U)

#define TCPP0203_PORT0_IANA_GPIO_CLK_ENABLE()       LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOC);
#define TCPP0203_PORT0_IANA_GPIO_CLK_DISABLE()      LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOC);
#define TCPP0203_PORT0_IANA_GPIO_PORT               GPIOC
#define TCPP0203_PORT0_IANA_GPIO_PIN                LL_GPIO_PIN_1
#define TCPP0203_PORT0_IANA_GPIO_MODE               LL_GPIO_MODE_ANALOG

#define TCPP0203_PORT0_VBUSC_GPIO_CLK_ENABLE()      LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
#define TCPP0203_PORT0_VBUSC_GPIO_CLK_DISABLE()     LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOA);
#define TCPP0203_PORT0_VBUSC_GPIO_PORT              GPIOA
#define TCPP0203_PORT0_VBUSC_GPIO_PIN               LL_GPIO_PIN_7
#define TCPP0203_PORT0_VBUSC_GPIO_MODE              LL_GPIO_MODE_ANALOG

#define TCPP0203_PORT0_VBUSPROV_GPIO_CLK_ENABLE()   LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
#define TCPP0203_PORT0_VBUSPROV_GPIO_CLK_DISABLE()  LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOA);
#define TCPP0203_PORT0_VBUSPROV_GPIO_PORT           GPIOA
#define TCPP0203_PORT0_VBUSPROV_GPIO_PIN            LL_GPIO_PIN_1
#define TCPP0203_PORT0_VBUSPROV_GPIO_MODE           LL_GPIO_MODE_ANALOG

#define TCPP0203_PORT0_VBUSCONS_GPIO_CLK_ENABLE()   LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
#define TCPP0203_PORT0_VBUSCONS_GPIO_CLK_DISABLE()  LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOA);
#define TCPP0203_PORT0_VBUSCONS_GPIO_PORT           GPIOA
#define TCPP0203_PORT0_VBUSCONS_GPIO_PIN            LL_GPIO_PIN_4
#define TCPP0203_PORT0_VBUSCONS_GPIO_MODE           LL_GPIO_MODE_ANALOG

#define USBPD_TCPP0203_VSENSE_RA                    130u /* VBUS voltage divider RA in kiloohm */
#define USBPD_TCPP0203_VSENSE_RB                    20u  /* VBUS voltage divider RB in kiloohm */

#define USBPD_TCPP0203_ISENSE_GA                    42u  /* Current measure gain In V/V */
#define USBPD_TCPP0203_ISENSE_RS                    22u  /* Current measure shunt resistor in milliohm */
/**
  * @}
  */

/**
  * @}
  */

/**
  * @}
  */

#ifdef __cplusplus
}
#endif

#endif /* USBPD_TCPP0203_CONF_H__*/

